1. Field of the Invention
The present invention relates to a master slice type semiconductor circuit device. More particularly, it relates to a gate array type large-scale integrated circuit device (gate array LSI) made of a master slice type semiconductor circuit device. The gate array LSI according to the present invention includes a logic block consisting of a plurality of basic gate circuit cells and memory circuits each consisting of a plurality of memory cells.
2. Description of the Related Art
A master slice type simiconductor circuit device is designed to facilitate short-run production meeting diverse customer requirements and is utilized, for example, for gate array LSI's.
In a master slice production method, a set of common processes are used to manufacture a master substrate for use in forming what will later be a variety of semiconductor devices. The master substrate is basically a plurality of basic cells, each cell consisting of transistors. The gate electrodes, sources, and drains of the transistors are uniformly formed on the master substrate. No wiring between the basic cells is provided at this time.
In the succeeding slice process, wiring is produced on the master substrate by using a wiring mask pattern. The wiring mask pattern is designed by a computer aided design (CAD) system to meet customer requirements.
In a gate array LSI, the basic cells, each consisting of a basic circuit, are arranged in a grid. The wiring between the basic cells is also designed by computer according to the logic circuit required by the customer. Recently, however, it has been proposed to provide specific memory blocks in a gate array LSI in addition to logic blocks. There are many problems with such a gate array LSI. First, there is limited flexibility in design since the capacity and circuit arrangement of such a memory circuit are set when the master slice is first produced and the capacity cannot be changed to meet customer requirements. Second, the wiring area is not effectively utilized, which obstructs miniaturization. To obtain a highly integrated gate array, it is important to minimize the wiring area and shorten the wiring length.